Optimization of Chip Interconnect Area by using Interconnect Length and Width
نویسندگان
چکیده
منابع مشابه
Optimization of Chip Interconnect Area by using Interconnect Length and Width
This paper presents methodologies that provide better correlation between the apriori and posteriori estimation of interconnect length, width, area and power. A method to generate random realistic benchmark circuits for analysis is implemented. A prediction model that predicts the length, width, area and power of the benchmark circuit is developed. The net list is passed through the placement a...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2010
ISSN: 0975-8887
DOI: 10.5120/897-1271